Search - dds verilog

[Other Embeded program] dds_drive.c

Description: DDS发生器NIOS .c文件,在NIOSII中可以配合Verilog代码生成的自定义外设产生DDS信号-DDS generator NIOS. C files, NIOSII can be in Verilog code generation with custom peripherals DDS generated signal
Platform: | Size: 4096 | Author: 白天 | Hits:

[Software Engineering] dds

Description: 基于FPGA的双路可移相任意波形发生器 Altera中国大学生电子设计文章竞赛获奖作品刊登-FPGA-based dual phase shifter can be arbitrary waveform generator Altera China Undergraduate Electronic Design Contest winning entries published articles
Platform: | Size: 1695744 | Author: 姜兆刚 | Hits:

[SCM] sgs32

Description: Verlog HDL 写得一款32路方波发生器，例子是4路可以自己加，相位可调，频率可调，占空比可调。具体参见readme.doc.此处只提供了源码包含顶层模块sgs32.v 子模块dds.v和pll设置模块altp.v及波形驱动文件-Verlog HDL write a 32 square-wave generator, for example, is able to add 4-way, phase adjustable, adjustable frequency, adjustable duty cycle. See readme.doc. Here only provide a source module that contains the top-level sub-modules sgs32.v settings dds.v and pll module altp.v and waveform-driven document
Platform: | Size: 59392 | Author: TTHR | Hits:

[VHDL-FPGA-Verilog] accumulator

Description: 实现累加器的verilog源码，广泛应用在通信电路设计中-The realization of accumulator Verilog source, widely used in communication circuit design
Platform: | Size: 1024 | Author: 文明 | Hits:

[VHDL-FPGA-Verilog] EDA

Description: 这里边有EDA设计常用模块的源代码，FFT,DDS PS2_keyboard，VGA等，有学FPGA的就参考一下吧-Here the design of commonly used modules have EDA source code, FFT, DDS PS2_keyboard, VGA and so on, have places on the FPGA reference yourself
Platform: | Size: 208896 | Author: li | Hits:

[Software Engineering] dds

Description: 自己收集的一些关于DDS的文章，主要讲述了DDS原理以及如何利用verilog实现DDS-To collect some of their articles on the DDS, the main principle on the DDS and how to use DDS to achieve verilog
Platform: | Size: 3298304 | Author: 刘小平 | Hits:

[SCM] dual_ram

Description: FPGA和双端口RAM的DDS任意波形发生器的实现-FPGA and dual-port RAM of the DDS Arbitrary Waveform Generator
Platform: | Size: 513024 | Author: 刘磊 | Hits:

[VHDL-FPGA-Verilog] learn_dds

Description: 基于quartus ii 9.0的简易dds波形发生器，可以产生正弦，方波，三角波，可变幅，可变频。非常适合学习使用，使用时请按自己的芯片和引脚设置-Quartus ii 9.0 Based on dds simple waveform generator can produce sine, square, triangle wave can be amplitude, frequency can be. Very suitable for learning to use, when used by their chip and pin set
Platform: | Size: 732160 | Author: 陈东旭 | Hits:

[Post-TeleCom sofeware systems] qam_64

Description: 64QAM调制,采用硬件语言verilog实现,其中调用了DDS的IP核-64QAM modulation, using language verilog hardware implementation, which is called the IP core of the DDS
Platform: | Size: 1024 | Author: zhujing | Hits:

[Compress-Decompress algrithms] asias_dds

Description: 一个简易的信号源，具有多种波形发生功能还有扫频，调制，频率计等相关功能-My project is on Direct Digital Synthesiser using Verilog HDL.This project is doing by me on july 2009 in summer training at NIT Kurukshetra, India. This DDS system generate the square wave, Triangular wave,Sine wave and saw wave with different frequency
Platform: | Size: 31744 | Author: david | Hits:

[Embeded Linux] 83390078DDS

Description: DDS的工作原理是以数控振荡器的方式产生频率、相位可控制的正弦波。电路一般包括基准时钟、频率累加器、相位累加器、幅度/相位转换电路、D/A转换器和低通滤波器（LPF）。频率累加器对输入信号进行累加运算，产生频率控制数据X（frequency data或相位步进量）。相位累加器由N位全加器和N位累加寄存器级联而成，对代表频率的2进制码进行累加运算，是典型的反馈电路，产生累加结果Y。幅度/相位转换电路实质上是一个波形寄存器，以供查表使用。读出的数据送入D/A转换器和低通滤波器。-DDS works the way we are digitally controlled oscillator frequency, phase controlled sine wave. Circuits generally include reference clock, frequency accumulator, phase accumulator, amplitude/phase converter circuit, D/A converter and low-pass filter (LPF). The frequency accumulator to accumulate the input signal operation to produce the frequency control data X (frequency data or phase stepping volume). From the N-bit phase accumulator and the N-bit full adder cascade accumulation register is made on behalf of the frequency of the two binary codes accumulation operation, is a typical feedback circuit, resulting in cumulative results of Y. Amplitude/phase converter circuit is essentially a waveform register for look-up table to use. Read out the data into the D/A converter and low pass filter.
Platform: | Size: 44032 | Author: 394177191 | Hits:

[VHDL-FPGA-Verilog] AD9954_test

Description: AD公司DDS芯片AD9954的Verilog测试程序-VerilogHDL test program of DDS chip--AD9954 ,producted by AD company
Platform: | Size: 2068480 | Author: ch | Hits:

[VHDL-FPGA-Verilog] MyDDS

Description: 利用查找表法编写的DDS的verilog程序，节省了利用IP核实现需要的资源，软件为ISE，-Prepared using look-up table method of verilog DDS program, save the use of IP core implementation requires resources, software for the ISE,
Platform: | Size: 2891776 | Author: 蜡笔 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 这个是我自己用VHDL语言写的两相数字信号发生器程序 D/A用的是DAC904-This is for my own use VHDL, written procedures for two-phase digital signal generator D/A using a DAC904
Platform: | Size: 1370112 | Author: 马骋 | Hits:

[VHDL-FPGA-Verilog] cordic

Description: 该程序使用Verilog语言，可以生成dds正余弦信号-The program uses the Verilog language, can generate sine and cosine signals dds
Platform: | Size: 6144 | Author: 王丽 | Hits:

[Other] dds

Description: 包含完整的dds产生的Verilog程序和test 文件-Contains the complete dds generated Verilog program and test files
Platform: | Size: 6110208 | Author: fqzxw | Hits:

[SCM] AD9910

Description: 这是AD9910 DDS芯片的verilog配置程序，经调试已成功，可以供大家参考。-AD9910 verilog configuation.
Platform: | Size: 1024 | Author: da niu | Hits:

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[Other Embeded program] dds_drive.c

[Software Engineering] dds

[SCM] sgs32

[VHDL-FPGA-Verilog] accumulator

[VHDL-FPGA-Verilog] EDA

[Software Engineering] dds

[SCM] dual_ram

[VHDL-FPGA-Verilog] learn_dds

[Post-TeleCom sofeware systems] qam_64

[Compress-Decompress algrithms] asias_dds

[Embeded Linux] 83390078DDS

[VHDL-FPGA-Verilog] AD9954_test

[VHDL-FPGA-Verilog] MyDDS

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] cordic

[Other] dds

[SCM] AD9910

[VHDL-FPGA-Verilog] Verilog

[VHDL-FPGA-Verilog] Verilog_FPGA_DDS

[VHDL-FPGA-Verilog] DDS

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